H8SSLASH2224 datasheet(390/1071 Pages) RENESAS

390 / 1071 page

Section 9 Data Transfer Controller (DTC)

Rev. 5.00 Aug 08, 2006 page 304 of 982

REJ09B0054-0500

4. Write 1 to the SWDTE bit and the vector number (H'60) to DTVECR. The write data is

H'E0.

5. Read DTVECR again and check that it is set to the vector number (H'60). If it is not, this

indicates that the write failed. This is presumably because an interrupt occurred between steps

3 and 4 and led to a different software activation. To activate this transfer, go back to step 3.

6. If the write was successful, the DTC is activated and a block of 128 bytes of data is

transferred.

7. After the transfer, an SWDTEND interrupt occurs. The interrupt handling routine should

clear the SWDTE bit to 0 and perform other wrap-up processing.

9.8

Usage Notes

9.8.1

Module Stop Mode Setting

DTC operation can be disabled or enabled using the module stop control register. The initial

setting is for DTC operation to be enabled. Register access is disabled by setting module stop

mode. Module stop mode cannot be set during DTC operation. For details, refer to section 24,

Power-Down Modes.

9.8.2

On-Chip RAM

The MRA, MRB, SAR, DAR, CRA, and CRB registers are all located in on-chip RAM. When the

DTC is used, the RAME bit in SYSCR should not be cleared to 0.

9.8.3

DTCE Bit Setting

For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. If all interrupts

are masked, multiple activation sources can be set at one time (only at the initial setting) by

writing data after executing a dummy read on the relevant register.

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