H8SSLASH2224 datasheet(387/1071 Pages) RENESAS

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Section 9 Data Transfer Controller (DTC)

Rev. 5.00 Aug 08, 2006 page 301 of 982

REJ09B0054-0500

9.5.7

Number of DTC Execution States

Table 9.6 lists execution status for a single DTC data transfer, and table 9.7 shows the number of

states required for each execution status.

Table 9.6

DTC Execution Status

Mode

Vector Read

Read/Write

Data Read

Data Write

Internal

Operations

Normal

Repeat

Block transfer

Legend:

N: Block size (initial setting of CRAH and CRAL)

Table 9.7

Number of States Required for Each Execution Status

Object to be Accessed

On-

Chip

RAM

On-

Chip

ROM

Internal I/O

Registers

External Devices

Bus width

Access states

Vector read SI





6 + 2 m 2

3 + m

Execution

Status

read/write SJ





Byte data read SK

3 + m

Word data read SK

6 + 2 m 2

3 + m

Byte data write SL

3 + m

Word data write SL

6 + 2 m 2

3 + m

Internal operation SM 1

Legend:

m: The number of wait states for accessing external devices.

The number of execution states is calculated from using the formula below. Note that

Σ is the sum

of all transfers activated by one activation event (the number in which the CHNE bit is set to 1,

plus 1).

Number of execution states = I · SI + Σ (J · SJ + K · SK + L · SL) + M · SM

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