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H8S/2224 Scheda tecnica(PDF) 396 Page - Renesas Technology Corp |
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H8S/2224 Scheda tecnica(HTML) 396 Page - Renesas Technology Corp |
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396 / 1071 page ![]() Section 10 I/O Ports Rev. 5.00 Aug 08, 2006 page 310 of 982 REJ09B0054-0500 10.1.2 Port 1 Data Register (P1DR) P1DR stores output data for port 1 pins. Bit Bit Name Initial Value R/W Description 7 P17DR 0 R/W 6 P16DR 0 R/W 5 P15DR 0 R/W 4 P14DR 0 R/W 3 P13DR 0 R/W 2 P12DR 0 R/W 1 P11DR 0 R/W 0 P10DR 0 R/W Output data for a pin is stored when the pin is specified as a general purpose I/O port. 10.1.3 Port 1 Register (PORT1) PORT1 shows the pin states. This register cannot be modified. Bit Bit Name Initial Value R/W Description 7P17 —* R 6P16 —* R 5P15 —* R 4P14 —* R 3P13 —* R 2P12 —* R 1P11 —* R 0P10 —* R If a port 1 read is performed while P1DDR bits are set to 1, the P1DR values are read. If a port 1 read is performed while P1DDR bits are cleared to 0, the pin states are read. Note: * Determined by the states of pins P17 to P10. |
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