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H8S/2224 Scheda tecnica(PDF) 409 Page - Renesas Technology Corp |
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H8S/2224 Scheda tecnica(HTML) 409 Page - Renesas Technology Corp |
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409 / 1071 page ![]() Section 10 I/O Ports Rev. 5.00 Aug 08, 2006 page 323 of 982 REJ09B0054-0500 10.4.2 Port 7 Data Register (P7DR) P7DR stores output data for port 7 pins. Bit Bit Name Initial Value R/W Description 7 P77DR 0 R/W 6 P76DR 0 R/W 5 P75DR 0 R/W 4 P74DR 0 R/W 3 P73DR 0 R/W 2 P72DR 0 R/W 1 P71DR 0 R/W 0 P70DR 0 R/W Output data for a pin is stored when the pin is specified as a general purpose I/O port. 10.4.3 Port 7 Register (PORT7) PORT7 shows the pin states. This register cannot be modified. Bit Bit Name Initial Value R/W Description 7P77 —* R 6P76 —* R 5P75 —* R 4P74 —* R 3P73 —* R 2P72 —* R 1P71 —* R 0P70 —* R If a port 1 read is performed while P7DDR bits are set to 1, the P7DR values are read. If a port 1 read is performed while P7DDR bits are cleared to 0, the pin states are read. Note: * Determined by the states of pins P77 to P70. |
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