H8SSLASH2224 datasheet(565/1071 Pages) RENESAS

565 / 1071 page

Section 13 Watchdog Timer (WDT)

Rev. 5.00 Aug 08, 2006 page 479 of 982

REJ09B0054-0500

13.6.3

Changing Value of CKS2 to CKS0

If bits CKS0 to CKS2 in TCSR are written to while the WDT is operating, errors could occur in

the incrementation. Software must be used to stop the watchdog timer (by clearing the TME bit to

0) before changing the value of bits CKS0 to CKS2.

13.6.4

Switching between Watchdog Timer Mode and Interval Timer Mode

If the mode is switched from watchdog timer to interval timer while the WDT is operating, errors

could occur in the incrementation. Software must be used to stop the watchdog timer (by clearing

the TME bit to 0) before switching the mode.

13.6.5 Internal Reset in Watchdog Timer Mode

This LSI is not reset internally if TCNT overflows while the RSTE bit is cleared to 0 during

watchdog timer operation, however TCNT_0 and TCSR_0 of the WDT_0 are reset.

TCNT, TCSR, or RSTCR cannot be written to for 132 states following an overflow. During this

period, any attempt to read the WOVF flag is not acknowledged. Accordingly, wait 132 states

after overflow to write 0 to the WOVF flag for clearing.

13.6.6

OVF Flag Clearing in Interval Timer Mode

When the OVF flag setting conflicts with the OVF flag reading in interval timer mode, writing 0

to the OVF bit may not clear the flag even though the OVF bit has been read while it is 1. If there

is a possibility that the OVF flag setting and reading will conflict, such as when the OVF flag is

polled with the interval timer interrupt disabled, read the OVF bit while it is 1 at least twice before

writing 0 to the OVF bit to clear the flag.

H8S/2224 Scheda tecnica(PDF) 565 Page - Renesas Technology Corp