H8SSLASH2224 datasheet(562/1071 Pages) RENESAS

Il numero della parte	H8S/2224

Spiegazioni elettronici	16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

PDF	1071 Pages

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Produttore elettronici	RENESAS [Renesas Technology Corp]

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Section 13 Watchdog Timer (WDT)

Rev. 5.00 Aug 08, 2006 page 476 of 982

REJ09B0054-0500

13.4.4

Timing of Setting Watchdog Timer Overflow Flag (WOVF)

With WDT_0 the WOVF bit in RSTCSR is set to 1 if TCNT overflows in watchdog timer mode.

If TCNT overflows while the RSTE bit in RSTCSR is set to 1, an internal is generated for the

entire chip. (The WOVI interrupt is not generated.) This timing is illustrated in figure 13.5.

TCNT

H'FF

H'00

Overflow signal

(internal signal)

WOVF

Internal reset

signal

518 states (WDT_0)

515/516 states (WDT_1)

Figure 13.5 Timing of WOVF Setting

13.5

Interrupt Sources

During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI).

The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be

cleared to 0 in the interrupt handling routine.

If an NMI interrupt request has been chosen in the watchdog timer mode, an NMI interrupt request

is generated when a TCNT overflow occurs.

Table 13.2 WDT Interrupt Source

Name

Interrupt Source

Interrupt Flag

WOVI

TCNT overflow (interval timer mode)

OVF

NMI

TCNT overflow (watchdog timer mode)

OVF

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