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H8S/2224 Scheda tecnica(PDF) 605 Page - Renesas Technology Corp

Il numero della parte H8S/2224
Spiegazioni elettronici  16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series
PDF  1071 Pages
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Produttore elettronici  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8S/2224 Scheda tecnica(HTML) 605 Page - Renesas Technology Corp

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Section 14 IEBus™ Controller (IEB) [H8S/2258 Group]
Rev. 5.00 Aug 08, 2006 page 519 of 982
REJ09B0054-0500
14.3.20 IEBus Transmit Error Flag Register (IETEF)
IETEF checks the source of a TxE interrupt indicated in IETSR. This register detects an overflow
of a maximum number of bytes in one frame, arbitration loss, underrun error, timing error, and
NAK reception.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 5
All 0
Reserved
These bits are always read as 0 and cannot be modified.
4
AL
0
R/W
Arbitration Loss
The IEB retransmits from the start bit for the number of
times specified by bits RN2 to Rn0 in IEMCR if the
arbitration has been lost in master communications. If the
arbitration has been lost for the specified number of times,
the AL and TxE flags are set to enter the wait state. If the
arbitration has been won within retransmit for the specified
number of times, this flag is not set to 1. This flag is set
only when the arbitration has been lost and the wait state is
entered.
[Setting condition]
When the arbitration has been lost during data
transmission and the transmission has been terminated
[Clearing condition]
When writing 0 after reading AL = 1
3
UE
0
R/W
Underrun Error
Indicates that an underrun error has occurred during data
transmission. The IEB detects an underrun error
occurrence when the IEB fetches data from IETBR while
the TxRDY flag is set to 1, and the IEB sets the TxE flag
and enters the wait state. Accordingly, when the TxRDY
flag is not cleared even if data is written to IETBR, an
underrun error occurs and data transmission is terminated.
Note that the TxRDY flag must be cleared in data
transmission by the CPU.
[Setting condition]
When the IEB loads data from IETBR to the transmit shift
register while the TxRDY flag is set to 1
[Clearing condition]
When writing 0 after reading UE = 1



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