H8SSLASH2224 datasheet(667/1071 Pages) RENESAS

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Section 15 Serial Communication Interface (SCI)

Rev. 5.00 Aug 08, 2006 page 581 of 982

REJ09B0054-0500

15.3.10 Serial Expansion Mode Register (SEMR_0)

SEMR_0 is an 8-bit register that expands SCI_0 functions; such as setting of the base clock,

selecting of the clock source, and automatic setting of the transfer rate.

Note: Supported only by the H8S/2239 Group only.

Bit

Bit Name

Initial

Value

R/W

Description

SSE

R/W

SCI_0 Select Enable

This bit enables or disables the SCI_0 select

function when an external clock is input in clocked

synchronous mode. When 1 is set to the

PG1/

IRQ7 pin, while the SCI_0 select function is

enabled, the TxD0 output becomes Hi-Z and the

SCK0 input in this LSI is fixed high making the

SCI_0 data transfer terminated. The SSE setting is

valid when the external clock input is selected

(CKE in SCR = 0) in clocked synchronous mode

(C/

A in SMR = 1).

0: SCI_0 select is disabled.

1: SCI_0 select is enabled.

When then PG1/

IRQ7 pin = 1, the TxD0 output

becomes Hi-Z and the SCK0 clock input is fixed

high.

6 to 4

—

Undefined

—

Reserved

These bits are always read as 0, and cannot be

modified.

ABCS

R/W

Asynchronous Base Clock Select

Selects the 1-bit-interval base clock in

asynchronous mode.

The ABCS setting is valid in asynchronous mode

(C/

A in SMR = 0).

0: Operates on a base clock with a frequency of 16

times the transfer rate.

1: Operates on a base clock with a frequency of 8

times the transfer rate.

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