H8SSLASH2224 datasheet(668/1071 Pages) RENESAS

668 / 1071 page

Section 15 Serial Communication Interface (SCI)

Rev. 5.00 Aug 08, 2006 page 582 of 982

REJ09B0054-0500

Bit

Bit Name

Initial

Value

R/W

Description

ACS2

ACS1

ACS0

R/W

Asynchronous Clock Source Select

When an average transfer rate is selected, the

base clock is set automatically regardless of the

ABCS value. Note that average transfer rates are

not supported for operating frequencies other than

10.667 MHz and 16 MHz.

The ACS0 to ACS0 settings are valid when the

external clock input is selected (CKE in SCR = 0)

in asynchronous mode (C/

A in SMR = 0).

000: External clock input

001: Selects the average transfer rate 115.152

kbps only for

φ = 10.667 MHz (operates on a

base clock with a frequency of 16 times the

transfer rate).

010: Selects the average transfer rate 460.606

kbps only for

φ = 10.667 MHz (operates on a

base clock with a frequency of 8 times the

transfer rate).

011: Reserved

100: TPU clock input (logical AND of TIOCA1 and

TIOCA2)

101: Selects the average transfer rate 115.196

kbps only for

φ = 16 MHz (operates on a

base clock with a frequency of 16 times the

transfer rate).

110: Selects the average transfer rate 460.784

kbps only for

φ = 16 MHz (operates on a

base clock with a frequency of 16 times the

transfer rate).

111: Selects the average transfer rate 720 kbps

only for

φ = 16 MHz (operates on a base

clock with a frequency of 8 times the transfer

rate).

Figures 15.3 and 15.4 show an example of the internal base clock when the average transfer rate is

selected.

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