H8SSLASH2224 datasheet(673/1071 Pages) RENESAS

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Section 15 Serial Communication Interface (SCI)

Rev. 5.00 Aug 08, 2006 page 587 of 982

REJ09B0054-0500

15.4.2

Receive Data Sampling Timing and Reception Margin in Asynchronous Mode

In asynchronous mode, the SCI operates on a base clock with a frequency of 16 times the transfer

rate. In reception, the SCI samples the falling edge of the start bit using the base clock, and

performs internal synchronization. Receive data is latched internally at the rising edge of the 8th

pulse of the base clock as shown in figure 15.6. Thus, the reception margin in asynchronous mode

is given by formula (1) below.

M = (0.5

−

)

− (L − 0.5) F −

+ F) × 100 [%]

− 0.5

... Formula (1)

Where M: Reception margin (%)

N: Bit rate ratio relative to clock (N = 16, but in the H8S/2239 Group N = 8 if ABCS in

SEMR_0 is set to 1.)

D: Clock duty (D = 0 to 1.0)

L: Frame length (L = 9 to 12)

F: Clock frequency deviation absolute value

Assuming values of F (absolute value of clock rate deviation) = 0, D (clock duty) = 0.5, and N

(ratio of bit rate to clock) = 16 in formula (1), the reception margin can be given by the formula.

M = {0.5 – 1/(2

× 16)} × 100 [%] = 46.875%

However, this is only the computed value, and a margin of 20% to 30% should be allowed for in

system design.

Note: Example for H8S/2239 Group with the ABCS bit in SEMR_0 set to a value other than 1.

When ABCS is set to 1, the clock frequency is 8 times the bit rate and sampling of

received data takes place at the fourth rising edge of the basic clock.

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