H8SSLASH2224 datasheet(711/1071 Pages) RENESAS

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Section 15 Serial Communication Interface (SCI)

Rev. 5.00 Aug 08, 2006 page 625 of 982

REJ09B0054-0500

15.10 Usage Notes

15.10.1 Module Stop Mode Setting

SCI operation can be disabled or enabled using the module stop control register. The initial setting

is for SCI operation to be halted. Register access is enabled by clearing module stop mode. For

details, refer to section 24, Power-Down Modes.

15.10.2 Break Detection and Processing (Asynchronous Mode Only)

When framing error (FER) detection is performed, a break can be detected by reading the RxD pin

value directly. In a break, the input from the RxD pin becomes all 0s, setting the FER flag, and

possibly the PER flag. Note that as the SCI continues the receive operation after receiving a break,

even if the FER flag is cleared to 0, it will be set to 1 again.

15.10.3 Mark State and Break Detection (Asynchronous Mode Only)

When TE is 0, the TxD pin is used as an I/O port whose direction (input or output) and level are

determined by DDR. This can be used to set the TxD pin to mark state (high level) or send a break

during serial data transmission. To maintain the communication line at mark state until TE is set to

1, set both DDR and DR to 1. As TE is cleared to 0 at this point, the TxD pin becomes an I/O port,

and 1 is output from the TxD pin. To send a break during serial transmission, first set PDR to 1

and DR to 0, and then clear TE to 0. When TE is cleared to 0, the transmitter is initialized

regardless of the current transmission state, the TxD pin becomes an I/O port, and 0 is output from

the TxD pin.

15.10.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)

Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if

the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting

transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared

to 0.

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