H8SSLASH2224 datasheet(778/1071 Pages) RENESAS

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Section 17 A/D Converter

Rev. 5.00 Aug 08, 2006 page 692 of 982

REJ09B0054-0500

17.3

The A/D converter has the following registers. For details on the module stop control register,

refer to section 24.1.2, Module Stop Control Registers A to C (MSTPCRA to MSTPCRC).

• A/D data register A (ADDRA)

• A/D data register B (ADDRB)

• A/D data register C (ADDRC)

• A/D data register D (ADDRD)

• A/D control/status register (ADCSR)

• A/D control register (ADCR)

17.3.1

A/D Data Registers A to D (ADDRA to ADDRD)

There are four 16-bit read-only ADDR registers; ADDRA to ADDRD, used to store the results of

A/D conversion. The ADDR registers, which store a conversion result for each channel, are shown

in table 17.2.

The converted 10-bit data is stored in bits 6 to 15. The lower 6 bits are always read as 0.

The data bus between the CPU and the A/D converter is 8 bits wide. The upper byte can be read

directly from the CPU, however the lower byte should be read via a temporary register. Therefore,

when reading the ADDR, read only the upper byte, or read in word unit.

Table 17.2 Analog Input Channels and Corresponding ADDR Registers

Analog Input Channel

Group 0 (CH2 = 0)

Group 1 (CH2 = 1)

A/D Data Register to be Stored the Results of

A/D Conversion

AN0

AN4

ADDRA

AN1

AN5

ADDRB

AN2

AN6

ADDRC

AN3

AN7

ADDRD

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