H8SSLASH2224 datasheet(779/1071 Pages) RENESAS

779 / 1071 page

Section 17 A/D Converter

Rev. 5.00 Aug 08, 2006 page 693 of 982

REJ09B0054-0500

17.3.2 A/D Control/Status Register (ADCSR)

ADCSR controls A/D conversion operations.

Bit

Bit Name

Initial

Value

R/W

Description

7ADF

R/(W)*

A/D End Flag

A status flag that indicates the end of A/D

conversion.

[Setting conditions]

• When A/D conversion ends in single mode

• When A/D conversion ends on all specified

channels in scan mode

[Clearing conditions]

• When 0 is written after reading ADF = 1

• When the data transfer controller (DTC) is

activated by an ADI interrupt and DISEL in DTC

is 0 with the transfer counter not being 0

ADIE

R/W

A/D Interrupt Enable

A/D conversion end interrupt (ADI) request enabled

when 1 is set

ADST

R/W

A/D Start

Clearing this bit to 0 stops A/D conversion, and the

A/D converter enters the wait state.

Setting this bit to 1 starts A/D conversion. In single

mode, this bit is cleared to 0 automatically when

conversion on the specified channel is complete. In

scan mode, conversion continues sequentially on

the specified channels until this bit is cleared to 0 by

software, a reset, software standby mode, hardware

standby mode, or module stop mode.

The ADST bit can be set to 1 by software, a timer

conversion start trigger, or the A/D external trigger

input pin (

ADTRG).

H8S/2224 Scheda tecnica(PDF) 779 Page - Renesas Technology Corp

H8S/2224 Scheda tecnica(HTML) 779 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL