H8SSLASH2224 datasheet(965/1071 Pages) RENESAS

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Section 27 Electrical Characteristics

Rev. 5.00 Aug 08, 2006 page 879 of 982

REJ09B0054-0500

(4) DMAC Timing

Table 27.20 lists the DMAC timing.

Table 27.20 DMAC Timing

Condition A (F-ZTAT version and masked ROM version):

VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V,

Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, φ = 2 to 16.0 MHz,

Ta = –20°C to +75°C (regular specifications)

Condition B (Masked ROM version): VCC = 2.2 V to 3.6 V, AVCC = 2.2 V to 3.6 V,

Vref = 2.2 V to AVCC, VSS = AVSS = 0 V, φ = 2 to 6.25 MHz,

Ta = –20°C to +75°C (regular specifications),

Ta = –40°C to +85°C (wide-range specifications)

Condition C (F-ZTAT version and masked ROM version):

VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V,

Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 10.0 MHz to

20.0 MHz, Ta = 20°C to +75°C (regular specifications),

Ta = 40°C to +85°C (wide-range specifications)

Condition A

Condition B

Condition C

Item

Symbol

Min

Max

Min

Max

Min

Max

Unit

Test Conditions

DREQ setup time

tDRQS



DREQ hold time

tDRQH



Figure 27.23

TEND delay time

tTED



Figure 27.22

DACK delay time 1

tDACD1



Figure 27.20

DACK delay time 2

tDACD2



Figure 27.21

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