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H8S/2224 Scheda tecnica(PDF) 968 Page - Renesas Technology Corp

Il numero della parte H8S/2224
Spiegazioni elettronici  16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series
PDF  1071 Pages
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Produttore elettronici  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8S/2224 Scheda tecnica(HTML) 968 Page - Renesas Technology Corp

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Section 27 Electrical Characteristics
Rev. 5.00 Aug 08, 2006 page 882 of 982
REJ09B0054-0500
Table 27.22 I2C Bus Timing
Conditions: VCC = 2.7 V to 3.6 V, VSS = 0 V, φ = 5 MHz to maximum operating frequency,
Ta = –20°C to +75°C
Item
Symbol
Min
Typ
Max
Unit
Test Conditions
SCL input cycle time
tSCL
12 tcyc

ns
SCL input high pulse width
tSCLH
3 tcyc

ns
Figure 27.34
SCL input low pulse width
tSCLL
5 tcyc

ns
SCL, SDA input rise time
tSr

7.5 tcyc* ns
SCL, SDA input fall time
tSf

300
ns
SCL, SDA input spike pulse
delete time
tSP

1 tcyc
ns
SDA input bus free time
tBUF
5 tcyc

ns
Operating condition input
hold time
tSTAH
3 tcyc

ns
Retransmitting operating
condition input setup time
tSTAS
3 tcyc

ns
Stop condition input setup
time
tSTOS
3 tcyc

ns
Data input setup time
tSDAS
0.5 tcyc

ns
Data input hold time
tSDAH
0

ns
SCL, SDA capacitor load
Cb

400
pF
Note:
* Maximum SCL and SDA input rise time 7.5 tcyc or 17.5 tcyc can be selected depending
on the clock that is used in the I
2C module. For detail, see section 16.6, Usage Notes.



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