H8SSLASH2224 datasheet(138/1071 Pages) RENESAS

138 / 1071 page

Section 1 Overview

Rev. 5.00 Aug 08, 2006 page 52 of 982

REJ09B0054-0500

Pin No.

Type

Symbol

TFP-100B

TFP-100BV

TFP-100G

TFP-100GV

FP-100B

FP-100BV

FP-100A*

FP-100AV*

BP-112*

BP-112V*

TBP-112A*

TBP-112AV*

4 I/O

Function

Address

bus

A23 to

37 to 15,

40 to 18,

L5, L4, L3,

L2, K5, K4,

K3, K2, K1,

J5, J4, J3,

J2, J1, H5,

H4, H3, H2,

H1, G4, G3,

G2, G1, F1

Output

Outputs Address.

Data bus

D15 to

100 to 96,

11 to 1

100, 99,

14 to 1

E4, E3, E1,

D4, D3, D2,

D1, C4, C2,

C1, B4, B3,

B2, B1, A3,

Input/

output

Used as the bidirectional data bus.

Bus

control

CS7

CS6

CS5

CS4

CS3

CS2

CS1

CS0

Output

Select signals for areas 7 to 0.

Output

When this pin is low, it indicates valid

address output on the address bus.

D10

Output

When this pin is low, it indicates that the

external address space is being read.

HWR

C11

Output

Strobe signal: Writes to the external

address bus to indicate valid data on the

upper data bus (D15 to D8).

LWR

Output

Strobe signal: Writes to the external bus to

indicate valid data on the lower data bus

(D7 to D0).

WAIT

C10

Input

Requests insertion of wait states in bus

cycle when accesses to the external three-

state address.

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