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H8S/2224 Scheda tecnica(PDF) 139 Page - Renesas Technology Corp |
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H8S/2224 Scheda tecnica(HTML) 139 Page - Renesas Technology Corp |
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139 / 1071 page ![]() Section 1 Overview Rev. 5.00 Aug 08, 2006 page 53 of 982 REJ09B0054-0500 Pin No. Type Symbol TFP-100B TFP-100BV TFP-100G TFP-100GV FP-100B FP-100BV FP-100A* 3 FP-100AV* 3 BP-112* 1 BP-112V* 1 TBP-112A* 4 TBP-112AV* 4 I/O Function DMA controller (DMAC)* 2 DREQ1 DREQ0 89 90 B6 D6 Input Request DMAC activation. (Supported only by the H8S/2239 Group.) TEND1 TEND0 87 88 C6 A6 Output Indicate that the DMAC has ended transmitting data. (Supported only by the H8S/2239 Group.) DACK1 DACK0 35 34 J5 H5 Output These pins function as single address transmitting acknowledge of DMAC. (Supported only by the H8S/2239 Group.) 16-bit timer- pulse unit (TPU) TCLKD TCLKC TCLKB TCLKA 41 39 37 36 44 42 40 39 H6 L6 K5 L5 Input These pins input an external clock. TIOCA0 TIOCB0 TIOCC0 TIOCD0 34 35 36 37 37 38 39 40 H5 J5 L5 K5 Input/ Output Pins for the TGRA_0 to TGRD_0 input capture input, output compare output, or PWM output. TIOCA1 TIOCB1 38 39 41 42 J6 L6 Input/ Output Pins for the TGRA _1 and TGRB_1 input capture input, output compare output, or PWM output. TIOCA2 TIOCB2 40 41 43 44 K6 H6 Input/ Output Pins for the TGRA _2 and TGRB_2 input capture input, output compare output, or PWM output. TIOCA3 TIOCB3 TIOCC3 TIOCD3 22 23 24 25 25 26 27 28 H3 J2 K1 J3 Input/ Output Pins for the TGRA_3 to TGRD_3 input capture input, output compare output, or PWM output. TIOCA4 TIOCB4 26 27 29 30 K2 L2 Input/ Output Pins for the TGRA_4 and TGRB_4 input capture input, output compare output, or PWM output. TIOCA5 TIOCB5 28 29 31 32 H4 K3 Input/ Output Pins for the TGRA_5 and TGRB_5 input capture input, output compare output, or PWM output. |
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