H8SSLASH2224 datasheet(160/1071 Pages) RENESAS

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Section 2 CPU

Rev. 5.00 Aug 08, 2006 page 74 of 982

REJ09B0054-0500

2.4.4

Condition-Code Register (CCR)

This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and

half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags.

Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC

instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch

(Bcc) instructions.

Bit

Bit Name

Initial Value

R/W

Description

R/W

Interrupt Mask Bit

Masks interrupts other than NMI when set to 1.

NMI is accepted regardless of the I bit setting.

The I bit is set to 1 by hardware at the start of an

exception-handling sequence. For details, refer

to section 5, Interrupt Controller.

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R/W

User Bit or Interrupt Mask Bit

Can be written and read by software using the

LDC, STC, ANDC, ORC, and XORC

instructions. This bit cannot be used as an

interrupt mask bit in this LSI.

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R/W

Half-Carry Flag

When the ADD.B, ADDX.B, SUB.B, SUBX.B,

CMP.B, or NEG.B instruction is executed, this

flag is set to 1 if there is a carry or borrow at bit

3, and cleared to 0 otherwise. When the

ADD.W, SUB.W, CMP.W, or NEG.W instruction

is executed, the H flag is set to 1 if there is a

carry or borrow at bit 11, and cleared to 0

otherwise. When the ADD.L, SUB.L, CMP.L, or

NEG.L instruction is executed, the H flag is set

to 1 if there is a carry or borrow at bit 27, and

cleared to 0 otherwise.

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R/W

User Bit

Can be written and read by software using the

LDC, STC, ANDC, ORC, and XORC

instructions.

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R/W

Negative Flag

Stores the value of the most significant bit of

data as a sign bit.

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