H8SSLASH2224 datasheet(165/1071 Pages) RENESAS

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Section 2 CPU

Rev. 5.00 Aug 08, 2006 page 79 of 982

REJ09B0054-0500

2.6

Instruction Set

The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function in

table 2.1.

Table 2.1

Instruction Classification

Function

Instructions

Size

Types

Data transfer

MOV

B/W/L

POP*

1, PUSH*1

W/L

LDM, STM

MOVFPE*

3, MOVTPE*3

ADD, SUB, CMP, NEG

B/W/L

Arithmetic

operations

ADDX, SUBX, DAA, DAS

INC, DEC

B/W/L

ADDS, SUBS

MULXU, DIVXU, MULXS, DIVXS

B/W

EXTU, EXTS

W/L

TAS*

Logic operations

AND, OR, XOR, NOT

B/W/L

Shift

SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR B/W/L

Bit manipulation

BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND,

BIAND, BOR, BIOR, BXOR, BIXOR

B14

Branch

Bcc*

2, JMP, BSR, JSR, RTS



System control

TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP



Block data transfer EEPMOV



Total: 65

Legend: B: Byte

W: Word

L: Longword

Notes: 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn,

@-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L

ERn, @-SP.

2. Bcc is the general name for conditional branch instructions.

3. Cannot be used in this LSI.

4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.

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