H8SSLASH2224 datasheet(175/1071 Pages) RENESAS

175 / 1071 page

Section 2 CPU

Rev. 5.00 Aug 08, 2006 page 89 of 982

REJ09B0054-0500

Table 2.10 Block Data Transfer Instructions

Instruction

Size

Function

EEPMOV.B



if R4L

≠ 0 then

Repeat @ER5+

→ @ER6+

R4L–1

→ R4L

Until R4L = 0

else next;

EEPMOV.W



if R4

≠ 0 then

Repeat @ER5+

→ @ER6+

R4–1

→ R4

Until R4 = 0

else next;

Transfers a data block. Starting from the address set in ER5, transfers

data for the number of bytes set in R4L or R4 to the address location set

in ER6.

Execution of the next instruction begins as soon as the transfer is

completed.

2.6.2

Basic Instruction Formats

The H8S/2000 CPU instructions consist of 2-byte (1-word) units. An instruction consists of an

operation field (op), a register field (r), an effective address extension (EA), and a condition field

(cc).

Figure 2.11 shows examples of instruction formats.

• Operation Field

Indicates the function of the instruction, the addressing mode, and the operation to be carried

out on the operand. The operation field always includes the first four bits of the instruction.

Some instructions have two operation fields.

• Register Field

Specifies a general register. Address registers are specified by 3 bits, and data registers by 3

bits or 4 bits. Some instructions have two register fields. Some have no register field.

• Effective Address Extension

8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement.

• Condition Field

Specifies the branching condition of Bcc instructions.

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