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H8S/2224 Scheda tecnica(PDF) 177 Page - Renesas Technology Corp

Il numero della parte H8S/2224
Spiegazioni elettronici  16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series
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Produttore elettronici  RENESAS [Renesas Technology Corp]
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H8S/2224 Scheda tecnica(HTML) 177 Page - Renesas Technology Corp

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Section 2 CPU
Rev. 5.00 Aug 08, 2006 page 91 of 982
REJ09B0054-0500
2.7.1
Register Direct—Rn
The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the
operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7
can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers.
2.7.2
Register Indirect—@ERn
The register field of the instruction code specifies an address register (ERn) which contains the
address of the operand on memory. If the address is a program instruction address, the lower 24
bits are valid and the upper 8 bits are all assumed to be 0 (H'00).
2.7.3
Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn)
A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn)
specified by the register field of the instruction, and the sum gives the address of a memory
operand. A 16-bit displacement is sign-extended when added.
2.7.4
Register Indirect with Post-Increment—@ERn+ or Register Indirect with Pre-
Decrement—@-ERn
Register indirect with post-increment—@ERn+: The register field of the instruction code
specifies an address register (ERn) which contains the address of a memory operand. After the
operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the
address register. The value added is 1 for byte access, 2 for word transfer instruction, or 4 for
longword transfer instruction. For the word or longword transfer instructions, the register value
should be even.
Register indirect with pre-decrement—@-ERn: The value 1, 2, or 4 is subtracted from an
address register (ERn) specified by the register field in the instruction code, and the result is the
address of a memory operand. The result is also stored in the address register. The value
subtracted is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer
instruction. For the word or longword transfer instructions, the register value should be even.
2.7.5
Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32
The instruction code contains the absolute address of a memory operand. The absolute address
may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long
(@aa:32). Table 2.12 indicates the accessible absolute address ranges.



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