H8SSLASH2224 datasheet(191/1071 Pages) RENESAS

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Section 3 MCU Operating Modes

Rev. 5.00 Aug 08, 2006 page 105 of 982

REJ09B0054-0500

3.2.2

System Control Register (SYSCR)

SYSCR is used to select the interrupt control mode and the detected edge for NMI, select the

MRES input pin enable or disable, and enables or disables on-chip RAM.

Bit

Bit Name

Initial Value R/W

Description

7—

R/W

Reserved

The write value should always be 0.

6—

—

Reserved

These bits are always read as 0 and cannot be

modified.

INTM1

INTM0

R/W

These bits select the control mode of the interrupt

controller. For details of the interrupt control modes,

see section 5.5.1, Interrupt Control Modes and

Interrupt Operation.

00: Interrupt control mode 0 (Interrupt is controlled by

I bit)

01: Setting prohibited

10: Interrupt control mode 2 (Interrupt is controlled by

I2 to I0 bits and IPR)

11: Setting prohibited

NMIEG

R/W

NMI Edge Select

Selects the valid edge of the NMI interrupt input.

0: An interrupt is requested at the falling edge of NMI

input

1: An interrupt is requested at the rising edge of NMI

input

MRESE

R/W

Manual Reset Select

Enables or disables the

MRES pin input.

0: The

MRES pin input (manual reset) is disabled

1: The

MRES pin input (manual reset) is enabled

The

MRES input pin can be used

1—

—

Reserved

These bits are always read as 0 and cannot be

modified.

RAME

R/W

RAM Enable

Enables or disables the on-chip RAM. The RAME bit

is initialized when the reset status is released.

0: On-chip RAM is disabled

1: On-chip RAM is enabled

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