H8SSLASH2224 datasheet(208/1071 Pages) RENESAS

208 / 1071 page

Section 4 Exception Handling

Rev. 5.00 Aug 08, 2006 page 122 of 982

REJ09B0054-0500

4.3.2

Reset Exception Handling

When the

RES or MRES pin goes low, this LSI enters the reset. To ensure that this LSI is reset,

hold the

RES pin low for at least 20 ms at power-up. To reset the chip during operation, hold the

RES or MRES pin low for at least 20 states. When the RES or MRES pin goes high after being

held low for the necessary time, this LSI starts reset exception handling as follows.

1. The internal state of the CPU and the registers of the on-chip peripheral modules are

initialized, the T bit in EXR is cleared to 0, and the I bits in EXR and CCR are set to 1.

2. The reset exception handling vector address is read and transferred to the PC, and program

execution starts from the address indicated by the PC.

Figures 4.1 shows an example of the reset sequence.

RES, MRES

High

Vector fetch

Internal

processing

Prefetch of first

program instruction

(1)(3) Reset exception handling vector address (at power on reset, (1) = H'000000, (3) = H'000002,

at manual reset, (1) = H'000004, (3) = H'000006)

(2)(4) Start address (contents of reset exception handling vector address)

(5)

Start address ((5) = (2) (4))

(6)

First program instruction

Address bus

HWR, LWR

D15 to D0

(1)

(2)

(4)

(6)

(3)

(5)

Note:

* Three states are inserted for waiting.

Figure 4.1 Reset Sequence (Mode 4)

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