H8SSLASH2224 datasheet(217/1071 Pages) RENESAS

Il numero della parte	H8S/2224

Spiegazioni elettronici	16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

PDF	1071 Pages

Scroll/Zoom	100%

Produttore elettronici	RENESAS [Renesas Technology Corp]

Homepage	http://www.renesas.com

Logo

217 / 1071 page

Section 5 Interrupt Controller

Rev. 5.00 Aug 08, 2006 page 131 of 982

REJ09B0054-0500

5.3.2

IRQ Enable Register (IER)

IER controls the enabling and disabling of interrupt requests IRQn (n = 7 to 0).

Bit

Bit Name

Initial

Value

R/W

Description

IRQ7E

R/W

IRQ7 Enable

The IRQ7 interrupt request is enabled when this bit is 1.

IRQ6E

R/W

IRQ6 Enable

The IRQ6 interrupt request is enabled when this bit is 1.

IRQ5E

R/W

IRQ5 Enable

The IRQ5 interrupt request is enabled when this bit is 1.

IRQ4E

R/W

IRQ4 Enable

The IRQ4 interrupt request is enabled when this bit is 1.

IRQ3E

R/W

IRQ3 Enable

The IRQ3 interrupt request is enabled when this bit is 1.

IRQ2E

R/W

IRQ2 Enable

The IRQ2 interrupt request is enabled when this bit is 1.

IRQ1E

R/W

IRQ1 Enable

The IRQ1 interrupt request is enabled when this bit is 1.

IRQ0E

R/W

IRQ0 Enable

The IRQ0 interrupt request is enabled when this bit is 1.

5.3.3

IRQ Sense Control Registers H and L (ISCRH and ISCRL)

The ISCR registers select the source that generates an interrupt request at pins

IRQn (n = 7 to 0).

Specifiable sources are the falling edge, rising edge, or both edge detection, and level sensing.

H8S/2224 Scheda tecnica(PDF) 217 Page - Renesas Technology Corp

H8S/2224 Scheda tecnica(HTML) 217 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL