H8SSLASH2224 datasheet(213/1071 Pages) RENESAS

213 / 1071 page

Section 5 Interrupt Controller

Rev. 5.00 Aug 08, 2006 page 127 of 982

REJ09B0054-0500

Section 5 Interrupt Controller

5.1

Features

This LSI controls interrupts with the interrupt controller. The interrupt controller has the following

features:

• Two interrupt control modes

 Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in

the system control register (SYSCR).

• Priorities settable with IPR

 An interrupt priority register (IPR) is provided for setting interrupt priorities. Eight priority

levels can be set for each module for all interrupts except NMI. NMI is assigned the

highest priority level of 8, also accepted (using nesting) during interrupt processing.

Additionally accepted during state 12 if Opcode = H'57F3.

• Independent vector addresses

 All interrupt sources are assigned independent vector addresses, making it unnecessary for

the source to be identified in the interrupt handling routine.

• Nine external interrupts

 NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling

edge can be selected for NMI. Falling edge, rising edge, or both edge detection, or level

sensing, can be independently selected for IRQ7 to IRQ0.

• DTC and DMAC* control

 The DTC and DMAC* can be activated by an interrupt request.

Note: * Supported only by the H8S/2239 Group.

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