H8SSLASH2224 datasheet(228/1071 Pages) RENESAS

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Section 5 Interrupt Controller

Rev. 5.00 Aug 08, 2006 page 142 of 982

REJ09B0054-0500

5.5

Operation

5.5.1

Interrupt Control Modes and Interrupt Operation

Interrupt operations in this LSI differ depending on the interrupt control mode.

NMI interrupts are accepted at all times except in the reset state and the hardware standby state. In

the case of IRQ interrupts and on-chip peripheral module interrupts, an enable bit is provided for

each interrupt. Clearing an enable bit to 0 disables the corresponding interrupt request. Interrupt

sources for which the enable bits are set to 1 are controlled by the interrupt controller.

Table 5.3 shows the interrupt control modes.

The interrupt controller performs interrupt control according to the interrupt control mode set by

the INTM1 and INTM0 bits in SYSCR, the priorities set in IPR, and the masking state indicated

by the I bit in the CPU’s CCR, and bits I2 to I0 in EXR.

Table 5.3

Interrupt Control Modes

SYSCR

Interrupt

Control Mode INTM1 INTM0

Priority Setting

Registers

Interrupt

Mask Bits Description



Interrupt mask control is

performed by the I bit.





Setting prohibited

IPR

I2 to I0

8-level interrupt mask control

is performed by bits I2 to I0.

8 priority levels can be set with

IPR.





Setting prohibited

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