H8SSLASH2224 datasheet(268/1071 Pages) RENESAS

268 / 1071 page

Section 7 Bus Controller

Rev. 5.00 Aug 08, 2006 page 182 of 982

REJ09B0054-0500

In byte access, whether the upper or lower data bus is used is determined by whether the address is

even or odd. The upper data bus is used for an even address, and the lower data bus for an odd

address.

D15

D8 D7

Upper data bus

Lower data bus

Byte size

Word size

1st bus cycle

2nd bus cycle

Longword

size

• Even address

Byte size

• Odd address

Figure 7.9 Access Sizes and Data Alignment Control (16-Bit Access Space)

7.6.2

Valid Strobes

Table 7.3 shows the data buses used and valid strobes for the access spaces.

In a read, the

RD signal is valid without discrimination between the upper and lower halves of the

data bus.

In a write, the

HWR signal is valid for the upper half of the data bus, and the LWR signal for the

lower half.

Table 7.3

Data Buses Used and Valid Strobes

Area

Access

Size

Read/

Write

Address

Valid Strobe

Upper Data Bus

(D15 to D8)

Lower Data Bus

(D7 to D0)

Byte

Read

—

Valid

Invalid

8-bit access

space

Write

—

HWR

Hi-Z

Byte

Read

Even

Valid

Invalid

Odd

Invalid

Valid

Write

Even

HWR

Valid

Hi-Z

Odd

LWR

Hi-Z

Valid

Word

Read

—

Valid

16-bit

access

space

Write

—

HWR, LWR

Valid

Notes: Hi-Z:

High impedance.

Invalid: Input state; input value is ignored.

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