H8SSLASH2224 datasheet(284/1071 Pages) RENESAS

Il numero della parte	H8S/2224

Spiegazioni elettronici	16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

PDF	1071 Pages

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Produttore elettronici	RENESAS [Renesas Technology Corp]

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Section 7 Bus Controller

Rev. 5.00 Aug 08, 2006 page 198 of 982

REJ09B0054-0500

Figure 7.24 shows the timing for transition to the bus-released state.

CPU

cycle

Address

Minimum

1 state

HWR, LWR

BREQ

BACK

High impedance

CSn

High impedance

Data bus

Address bus

[1]

[2]

[3]

[4]

[5]

[1]

Low level of

BREQ pin is sampled at rise of T2 state.

[2]

BACK pin is driven low at end of CPU read cycle, releasing bus to external bus

master.

[3]

BREQ pin state is still sampled in external bus released state.

[4]

High level of

BREQ pin is sampled.

[5]

BACK pin is driven high, ending bus release cycle.

CPU cycle

External bus released state

Note : n = 7 to 0

Figure 7.24 Bus-Released State Transition Timing

7.9.1

Bus Release Usage Note

When MSTPCR is set to H'FFFFFF and transmitted to sleep mode, the external bus release does

not function. To activate the external bus release in sleep mode, do not set MSTPCR to H'FFFFFF.

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