H8SSLASH2224 datasheet(285/1071 Pages) RENESAS

285 / 1071 page

Section 7 Bus Controller

Rev. 5.00 Aug 08, 2006 page 199 of 982

REJ09B0054-0500

7.10

Bus Arbitration

This LSI has a bus arbiter that arbitrates bus master operations.

There are three bus masters, the CPU, DMAC*, and DTC, which perform read/write operations

when they have possession of the bus. Each bus master requests the bus by means of a bus request

signal. The bus arbiter determines priorities at the prescribed timing, and permits use of the bus by

means of a bus request acknowledge signal. The selected bus master then takes possession of the

bus and begins its operation.

Note: * Supported only by the H8S/2239 Group.

7.10.1

Operation

The bus arbiter detects the bus masters' bus request signals, and if the bus is requested, sends a bus

request acknowledge signal to the bus master making the request. If there are bus requests from

more than one bus master, the bus request acknowledge signal is sent to the one with the highest

priority. When a bus master receives the bus request acknowledge signal, it takes possession of the

bus until that signal is canceled.

The order of priority of the bus masters is as follows:

(High) DMAC* > DTC > CPU (Low)

An internal bus access by an internal bus master, and external bus release, can be executed in

parallel.

In the event of simultaneous external bus release request, and internal bus master external access

request generation, the order of priority is as follows:

(High) External bus release > Internal bus master external access (Low)

Note: * Supported only by the H8S/2239 Group.

H8S/2224 Scheda tecnica(PDF) 285 Page - Renesas Technology Corp