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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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H8S/2224 Scheda tecnica(PDF) 290 Page - Renesas Technology Corp |
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H8S/2224 Scheda tecnica(HTML) 290 Page - Renesas Technology Corp |
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290 / 1071 page  Section 8 DMA Controller (DMAC) Rev. 5.00 Aug 08, 2006 page 204 of 982 REJ09B0054-0500 A block diagram of the DMAC is shown in figure 8.1. Internal address bus Address buffer Processor Internal interrupts TGI0A TGI1A TGI2A TGI3A TGI4A TGI5A TXI0 RXI0 TXI1 RXI1 ADI External pins DREQ0 DREQ1 TEND0 TEND1 DACK0 DACK1 Interrupt signals DEND0A DEND0B DEND1A DEND1B Control logic DMAWER DMACR_1B DMACR_1A DMACR_0B DMACR_0A DMATCR DMABCR Data buffer Internal data bus MAR_0AH IOAR_0A ETCR_0A MAR_0BH IOAR_0B ETCR_0B MAR_1AH IOAR_1A ETCR_1A MAR_1BH MAR_0AL MAR_0BL MAR_1AL MAR_1BL IOAR_1B ETCR_1B Legend: DMAWER: DMA write enable register DMATCR: DMA terminal control register DMABCR: DMA band control register (for all channels) DMACR: DMA control register MAR: Memory address register IOAR: I/O address register ETCR: Execute transfer count register Figure 8.1 Block Diagram of DMAC |
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