H8SSLASH2224 datasheet(291/1071 Pages) RENESAS

291 / 1071 page

Section 8 DMA Controller (DMAC)

Rev. 5.00 Aug 08, 2006 page 205 of 982

REJ09B0054-0500

8.2

Input/Output Pins

Table 8.1 shows the pin configuration of the interrupt controller.

Table 8.1

Pin Configuration

Channel

Pin Name

Symbol

I/O

Function

DMA request 0

DREQ0

Input

Channel 0 external request

DMA transfer acknowledge 0

DACK0

Output

Channel 0 single address

transfer acknowledge

DMA transfer end 0

TEND0

Output

Channel 0 transfer end

DMA request 1

DREQ1

Input

Channel 1 external request

DMA transfer acknowledge 1

DACK1

Output

Channel 1 single address

transfer acknowledge

DMA transfer end 1

TEND1

Output

Channel 1 transfer end

8.3

• Memory address register_0AH (MAR_0AH)

• Memory address register_0AL (MAR_0AL)

• I/O address register_0A (IOAR_0A)

• Transfer count register_0A (ETCR_0A)

• Memory address register_0BH (MAR_0BH)

• Memory address register_0BL (MAR_0BL)

• I/O address register_0B (IOAR_0B)

• Transfer count register_0B (ETCR_0B)

• Memory address register_1AH (MAR_1AH)

• Memory address register_1AL (MAR_1AL)

• I/O address register_1A (IOAR_1A)

• Transfer count register_1A (ETCR_1B)

• Memory address register_1BH (MAR_1BH)

• Memory address register_1BL (MAR_1BL)

• I/O address register_1B (IOAR_1B)

• Transfer count register_1B (ETCR_1B)

• DMA control register_0A (DMACR_0A)

• DMA control register_0B (DMACR_0B)

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