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ATtiny261-ESSZ Scheda tecnica(PDF) 118 Page - ATMEL Corporation |
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ATtiny261-ESSZ Scheda tecnica(HTML) 118 Page - ATMEL Corporation |
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118 / 227 page ![]() 118 7753C–AVR–07/09 ATtiny261/ATtiny461/ATtiny861 The automatic action programmed in COM1A1 and COM1A0 takes place as if a compare match had occurred, but no interrupt is generated. The FOC1A bit is always read as zero. • Bit 2 - FOC1B: Force Output Compare Match 1B The FOC1B bit is only active when the PWM1B bit specify a non-PWM mode. Writing a logical one to this bit forces a change in the Waveform Output (OCW1B) and the Out- put Compare pin (OC1B) according to the values already set in COM1B1 and COM1B0. If COM1B1 and COM1B0 written in the same cycle as FOC1B, the new settings will be used. The Force Output Compare bit can be used to change the output pin value regardless of the timer value. The automatic action programmed in COM1B1 and COM1B0 takes place as if a compare match had occurred, but no interrupt is generated. The FOC1B bit is always read as zero. • Bit 1 - PWM1A: Pulse Width Modulator A Enable When set (one) this bit enables PWM mode based on comparator OCR1A • Bit 0 - PWM1B: Pulse Width Modulator B Enable When set (one) this bit enables PWM mode based on comparator OCR1B. 16.11.2 TCCR1B – Timer/Counter1 Control Register B • Bit 7 - PWM1X: PWM Inversion Mode When this bit is set (one), the PWM Inversion Mode is selected and the Dead Time Generator outputs, OC1x and OC1x are inverted. • Bit 6 - PSR1: Prescaler Reset Timer/Counter1 When this bit is set (one), the Timer/Counter1 prescaler (TCNT1 is unaffected) will be reset. The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have no effect. This bit will always read as zero. • Bits 5,4 - DTPS11, DTPS10: Dead Time Prescaler Bits The Timer/Counter1 Control Register B is a 8-bit read/write register. The dedicated Dead Time prescaler in front of the Dead Time Generator can divide the Timer/Counter1 clock (PCK or CK) by 1, 2, 4 or 8 providing a large range of dead times that can be generated. The Dead Time prescaler is controlled by two bits DTPS11 and DTPS10 from the Dead Time Prescaler register. These bits define the division factor of the Dead Time prescaler. The division factors are given in Table 16-14. Bit 76543210 0x2F (0x4F) PWM1X PSR1 DTPS11 DTPS10 CS13 CS12 CS11 CS10 TCCR1B Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00000000 |
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