ATtiny261-ESSZ datasheet(119/227 Pages) ATMEL

119 / 227 page

119

7753C–AVR–07/09

ATtiny261/ATtiny461/ATtiny861

• Bits 3.. 0 - CS13, CS12, CS11, CS10: Clock Select Bits 3, 2, 1, and 0

The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1.

The Stop condition provides a Timer Enable/Disable function.

16.11.3

TCCR1C – Timer/Counter1 Control Register C

• Bits 7,6 - COM1A1S, COM1A0S: Comparator A Output Mode, Bits 1 and 0

These bits are the shadow bits of the COM1A1 and COM1A0 bits that are described in the sec-

tion “TCCR1A – Timer/Counter1 Control Register A” on page 115.

Table 16-14. Division factors of the Dead Time prescaler

DTPS11

DTPS10

Prescaler divides the T/C1 clock by

1x (no division)

Table 16-15. Timer/Counter1 Prescaler Select

CS13

CS12

CS11

CS10

Asynchronous Clocking Mode

Synchronous Clocking Mode

0000T/C1 stopped

T/C1 stopped

0001PCK

0010PCK/2

CK/2

0011PCK/4

CK/4

0100PCK/8

CK/8

0101PCK/16

CK/16

0110PCK/32

CK/32

0111PCK/64

CK/64

1000PCK/128

CK/128

1001PCK/256

CK/256

1010PCK/512

CK/512

1011PCK/1024

CK/1024

1100PCK/2048

CK/2048

1101PCK/4096

CK/4096

1110PCK/8192

CK/8192

1111PCK/16384

CK/16384

Bit

76543210

0x27 (0x47)

COM1A1S COM1A0S COM1B1S COM1B0S

COM1D1

COM1D0

FOC1D

PWM1D

TCCR1C

Read/Write

R/W

Initial value

00000000

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