ATtiny261-ESSZ datasheet(122/227 Pages) ATMEL

122 / 227 page

122

7753C–AVR–07/09

ATtiny261/ATtiny461/ATtiny861

• Bit 3 - FPAC1: Fault Protection Analog Comparator Enable

When written logic one, this bit enables the Fault Protection function in Timer/Counter1 to be

triggered by the Analog Comparator. The comparator output is in this case directly connected to

the Fault Protection front-end logic, making the comparator utilize the noise canceler and edge

select features of the Timer/Counter1 Fault Protection interrupt. When written logic zero, no con-

nection between the Analog Comparator and the Fault Protection function exists. To make the

comparator trigger the Timer/Counter1 Fault Protection interrupt, the FPIE1 bit in the

Timer/Counter1 Control Register D (TCCR1D) must be set.

• Bit 2- FPF1: Fault Protection Interrupt Flag

When the FPIE1 bit is set (one), the Fault Protection Interrupt is enabled. Activity on the pin will

cause an interrupt request even, if the Fault Protection pin is configured as an output. The corre-

sponding interrupt of Fault Protection Interrupt Request is executed from the Fault Protection

Interrupt Vector. The bit FPF1 is cleared by hardware when executing the corresponding inter-

rupt handling vector. Alternatively, FPF1 is cleared after a synchronization clock cycle by writing

a logical one to the flag. When the SREG I-bit, FPIE1 and FPF1 are set, the Fault Interrupt is

executed.

• Bits 1:0 - WGM11, WGM10: Waveform Generation Mode Bits

This bit associated with the PWMx bits control the counting sequence of the counter, the source

for type of waveform generation to be used, see Table 16-19. Modes of operation supported by

the Timer/Counter1 are: Normal mode (counter), Fast PWM Mode, Phase and Frequency Cor-

rect PWM and PWM6 Modes.

16.11.5

TCCR1E – Timer/Counter1 Control Register E

• Bits 7:6 - Res: Reserved Bits

These bits are reserved bits in the ATtiny261/461/861 and always reads as zero.

• Bits 5:0 – OC1OE5:OC1OE0: Output Compare Override Enable Bits

These bits are the Output Compare Override Enable bits that are used to connect or disconnect

the Output Compare Pins in PWM6 Modes with an instant response on the corresponding Out-

put Compare Pins.

Table 16-19. Waveform Generation Mode Bit Description

PWM1x

WGM11..10 Timer/Counter Mode of Operation

TOP

Update of

OCR1x at

TOV1 Flag

Set on

Normal

OCR1C

Immediate

TOP

Fast PWM

OCR1C

TOP

Phase and Frequency Correct PWM

OCR1C

BOTTOM

PWM6 / Single-slope

OCR1C

TOP

PWM6 / Dual-slope

OCR1C

BOTTOM

Bit

76543210

0x00 (0x20)

OC1OE5

OC1OE4

OC1OE3

OC1OE2

OC1OE1

OC1OE0

TCCR1E

Read/Write

R/W

Initial value

00000000

ATtiny261-ESSZ Scheda tecnica(PDF) 122 Page - ATMEL Corporation

ATtiny261-ESSZ Scheda tecnica(HTML) 122 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL