CDPCLK4 datasheet(257/274 Pages) ALTERA

257 / 274 page

Chapter 11: SEU Mitigation in the Cyclone III Device Family

11–5

Error Detection Timing

December 2011

Altera Corporation

Cyclone III Device Handbook

Volume 1

Figure 11–1 shows the block diagram of the error detection block and the two related

32-bit registers: the signature register and the storage register.

Table 11–4 lists the registers shown in Figure 11–1.

Error Detection Timing

When the error detection CRC feature is enabled through the Quartus II software, the

device automatically activates the CRC process upon entering user mode after

configuration and initialization is complete.

The CRC_ERROR pin is driven low until the error detection circuitry has detected a

corrupted bit in the previous CRC calculation. After the pin goes high, it remains high

during the next CRC calculation. This pin does not log the previous CRC calculation.

If the new CRC calculation does not contain any corrupted bits, the CRC_ERROR pin is

driven low. The error detection runs until the device is reset.

The error detection circuitry runs off an internal configuration oscillator with a divisor

that sets the maximum frequency.

Figure 11–1. Error Detection Block Diagram

Control Signals

Error Detection

State Machine

32-bit Storage

Compute & Compare

CRC

32-bit Signature

Table 11–4. Error Detection Registers

Function

32-bit signature

This register contains the CRC signature. The signature register contains the result of the user

mode calculated CRC value compared against the pre-calculated CRC value. If no errors are

detected, the signature register is all zeros. A non-zero signature register indicates an error in the

configuration CRAM contents.

The CRC_ERROR signal is derived from the contents of this register.

32-bit storage register

This register is loaded with the 32-bit pre-computed CRC signature at the end of the configuration

stage. The signature is then loaded into the 32-bit CRC circuit (called the Compute and Compare

CRC block, as shown in Figure 11–1) during user mode to calculate the CRC error. This register

forms a 32-bit scan chain during execution of the CHANGE_EDREG JTAG instruction. The

CHANGE_EDREG

JTAG instruction can change the content of the storage register. Therefore, the

functionality of the error detection CRC circuitry is checked in-system by executing the instruction

to inject an error during the operation. The operation of the device is not halted when issuing the

CHANGE_EDREG

instruction.

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