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PIIX Scheda tecnica(PDF) 85 Page - Intel Corporation |
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PIIX Scheda tecnica(HTML) 85 Page - Intel Corporation |
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85 / 122 page ![]() E 82371FB (PIIX) AND 82371SB (PIIX3) 85 take effect from the beginning of the next frame. This register is reset upon a Host Controller Reset or Global Reset. Software must maintain a copy of its value for reprogramming if necessary. Bit Description 7 Reserved. 6:0 SOF Timing Value. Guidelines for the modification of frame time are contained in Chapter 7 of the USB Specification. The SOF counter is initialized to a count of 11936. The SOF cycle time (number of SOF counter clock periods to generate a SOF) is equal to 11936 + value in this field. The default value is decimal 64 which gives a SOF count value of 12000. For a 12 MHz SOF counter clock input, this produces a 1 ms Frame period. The following table indicates what SOF Timing Value to program into this field for a certain frame. Frame Length SOF Reg. Value (# 12Mhz Clocks) (decimal) (decimal) 11936 0 11937 1 . . . . 11999 63 12000 64 12001 65 . . . . 12062 126 12063 127 2.8.7. PORTSC Port Status and Control Register I/O Address: Base + (10 −11h)Port 1 Base + (12 −13h) Port 2 Default: 0000h Access: Read/Write (WORD writeable only) Size: 16 bits After a Power-up and after a RESET, the initial conditions of a port are: No device connected, Port disabled, and the bus line status is 00 (single-ended zero). Note: If a device is attached, the port state will transition to the attached state and system software will process this as with any status change notification. It may take up to 64 USB bit times for the port transition to occur. Note that, if the Host Controller is in Global Suspend mode, then, if any of bits [6,3,1] gets set, the Host Controller will signal a resume. Refer to Chapter 11 of the USB Specification for details on hub operation. |
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