PIIX datasheet(11/122 Pages) INTEL

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82371FB (PIIX) AND 82371SB (PIIX3)

Signal Name

Type

Description

MIRQ0/IRQ0

(PIIX3 Only)

MIRQ[1:0]

(PIIX Only)

I/O

MOTHERBOARD DEVICE INTERRUPT REQUEST: The MIRQx

signals can be internally connected to interrupts IRQ[15,14,12:9,7:3].

Each MIRQx line has a separate Route Control Register. If MIRQx and

PIRQx# are steered to the same ISA interrupt, the device connected to

the MIRQx should produce active high, level interrupts. The

MIRQ0/IRQ0 signal has two functions (for PIIX3 only), depending on

the programming of the IRQ0 Enable bit (MIRQ0 Register). In the

systems that include the PIIX3 and IOAPIC, the MIRQ0/IRQ0 pin will

function as the IRQ0 output and should be connected to the INTIN2

input of the IOAPIC. The interrupt from the Secondary IDE Channel

should be connected to the IRQ15 input on PIIX3 and to the INTIN15

input on the IOAPIC. In the systems that include the PIIX3 only, the

interrupt from the Secondary IDE Channel should be connected to the

MIRQ0/IRQ0 input.

If an MIRQ line is steered to a given IRQ input to the internal 8259, the

corresponding ISA IRQ is masked, unless the Route Control register is

programmed to allow the interrupts to be shared. This should only be

done if the device connected to the MIRQ line and the device

connected to the ISA IRQ line both produce active high, level

interrupts.

MIRQ0 can be configured as an output to connect the internal IRQ0

signal to an external IO-APIC.

1.3.

IDE Interface Signals

Signal Name

Type

Description

DD[15:0]/

PCS#,

SBHE#,

SA[19:8]

APICCS#

(PIIX3)

I/O

DISK DATA: These signals directly drive the corresponding signals on

up to two IDE connectors (primary and secondary). In addition, these

signals are buffered (using 2xALS245’s on the motherboard) to produce

the SA[19:8], PCS#, and SBHE# signals (see separate descriptions).

For the PIIX3, DD14 is buffered to produce APICCS#

DIOR#

DISK I/O READ: This signal directly drives the corresponding signal on

up to two IDE connectors (primary and secondary).

DIOW#

DISK I/O WRITE: This signal directly drives the corresponding signal on

up to two IDE connectors (primary and secondary).

DDRQ[1:0]

DISK DMA REQUEST: These input signals are directly driven from the

DRQ signals on the primary (DDRQ0) and secondary (DDRQ1) IDE

connectors. They are used in conjunction with the PCI Bus master IDE

function and are not associated with any ISA-Compatible DMA channel.

DDAK[1:0]#

DISK DMA ACKNOWLEDGE: These signals directly drive the DAK#

signals on the primary (DDAK0# ) and secondary (DDAK1#) IDE

connectors. These signals are used in conjunction with the PCI Bus

master IDE function and are not associated with any ISA-Compatible

DMA channel.

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