PIIX datasheet(3/122 Pages) INTEL

3 / 122 page

82371FB (PIIX) AND 82371SB (PIIX3)

CONTENTS

PAGE

REVISION HISTORY...................................................................................................................................... 7

1.0. SIGNAL DESCRIPTION .......................................................................................................................... 9

1.1. PCI Interface Signals ........................................................................................................................... 9

1.2. Motherboard I/O Device Interface Signals .......................................................................................... 10

1.3. IDE Interface Signals ......................................................................................................................... 11

1.4. ISA Interface Signals.......................................................................................................................... 13

1.5. DMA Signals ...................................................................................................................................... 15

1.6. Timer/Counter Signals........................................................................................................................ 15

1.7. Interrupt Controller Signals................................................................................................................. 16

1.8. System Power Management (SMM) Signals ...................................................................................... 16

1.9. X-Bus Signals .................................................................................................................................... 17

1.10. APIC Bus Signals (PIIX3 Only) ........................................................................................................ 18

1.11. Universal Serial Bus Signals (PIIX3 Only) ........................................................................................ 19

1.12. System Reset Signals ...................................................................................................................... 19

1.13. Test Signals ..................................................................................................................................... 20

1.14. Power and Ground Signals............................................................................................................... 20

1.15. Signal State During Reset ................................................................................................................ 21

2.0. REGISTER DESCRIPTION ................................................................................................................... 22

2.1. Register Access ................................................................................................................................. 22

2.2. PCI Configuration Registers—PCI To ISA Bridge (Function 0)........................................................... 31

2.2.1. VID—VENDOR IDENTIFICATION REGISTER (Function 0)........................................................ 31

2.2.2. DID—DEVICE IDENTIFICATION REGISTER (Function 0) ......................................................... 31

2.2.3. PCICMD—COMMAND REGISTER (Function 0) ......................................................................... 31

2.2.4. PCISTS—PCI DEVICE STATUS REGISTER (Function 0) .......................................................... 32

2.2.5. RID—REVISION IDENTIFICATION REGISTER (Function 0)...................................................... 33

2.2.6. CLASSC

CLASS CODE REGISTER (Function 0)..................................................................... 33

2.2.7. HEDT—HEADER TYPE REGISTER (Function 0) ....................................................................... 33

2.2.8. IORT—ISA I/O RECOVERY TIMER REGISTER (Function 0) ..................................................... 33

2.2.9. XBCS—X-BUS CHIP SELECT REGISTER (Function 0) ............................................................. 34

2.2.10. PIRQRC[A:D]—PIRQx ROUTE CONTROL REGISTERS (Function 0)...................................... 36

2.2.11. TOM—TOP OF MEMORY REGISTER (Function 0).................................................................. 36

2.2.12. MSTAT—MISCELLANEOUS STATUS REGISTER (Function 0)............................................... 37

2.2.13. MBIRQ[1:0]—MOTHERBOARD DEVICE IRQ ROUTE CONTROL REGISTERS (Function 0) .. 39

2.2.14. MBDMA[1:0]—MOTHERBOARD DEVICE DMA CONTROL REGISTERS (Function 0) ............ 40

2.2.15. PCSC—PROGRAMMABLE CHIP SELECT CONTROL REGISTER (Function 0) ..................... 40

2.2.16. APICBASE—APIC BASE ADDRESS RELOCATION REGISTER (Function 0) (PIIX3 Only) ..... 41

2.2.17. DLC—DETERMINISTIC LATENCY CONTROL REGISTER (Function 0) (PIIX3 Only) ............. 42

2.2.18. SMICNTL—SMI CONTROL REGISTER (Function 0)................................................................ 43

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