PIIX datasheet(55/122 Pages) INTEL

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82371FB (PIIX) AND 82371SB (PIIX3)

2.4.4.

DEVICE STATUS REGISTER (Function 2) (PIIX3)

Address Offset:

−07h

Default Value:

0280h

Attribute:

Read/Write

DSR is a 16-bit status register that reports the occurrence of a PCI master-abort by the USB HC module or a

PCI target-abort when the Serial Bus module is a master. The register also indicates the USB HC module

DEVSEL# signal timing that is hardwired in the USB HC module. The DS fields are shown in the table below.

Bit

Description

Detected Parity Error (PERR). (Not Implemented) Read as 0.

SERR# Status (SERRS). (Not Implemented) Read as 0.

Master-Abort Status (MAS)

R/WC:. When the Serial Bus module generates a master-abort,

MA is set to a 1. Software sets MA to 0 by writing a 1 to this bit.

Received Target-Abort Status (RTA)

R/WC. When the Serial Bus module is a master on

the PCI Bus and receives a target-abort, this bit is set to a 1. Software resets RTA to 0 by

writing a 1 to this bit.

Signaled Target-Abort Status (STA)

R/WC. This bit is set when the Serial Bus module

function is targeted with a transaction that the Serial Bus module terminates with a target abort.

Software resets STA to 0 by writing a 1 to this bit.

10:9

DEVSEL# Timing Status (DEVT)

RO. This 2-bit field defines the timing for DEVSEL#

assertion. These read only bits indicate the PIIX3’s DEVSEL# timing when performing a

positive decode. Since the PIIX3 always generate the DEVSEL# with medium timing,

DEVT=01. This DEVSEL# timing does not include Configuration cycles.

Data Parity Detected (DPD). (Not Implemented). Read as 0.

Fast Back to Back Capable (FBC)

RO. Hardwired to 1. This bit indicates to the PCI Master

that Serial Bus module as a target is capable of accepting fast back-to-back transactions.

6:0

Reserved. Read as 0's.

2.4.5.

RID

REVISION IDENTIFICATION REGISTER (Function 2) (PIIX3)

Address Offset:

08h

Default Value:

Refer to applicable specification update document

Attribute:

Read Only

This 8-bit register contains device stepping information. Writes to this register have no effect.

Bit

Description

7:0

Revision ID Byte. The register is hardwired to the default value during manufacturing.

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