PIIX datasheet(62/122 Pages) INTEL

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82371FB (PIIX) AND 82371SB (PIIX3)

Bit

Description

Address Increment/Decrement Select. 0=Increment; 1=Decrement.

Autoinitialize Enable. 1=Enable; 0=Disable.

3:2

DMA Transfer Type. When Bits [7:6]=11, the transfer type bits are irrelevant.

Bits[3:2]

Transfer Type

Verify transfer

Write transfer

Read transfer

Illegal

1:0

DMA Channel Select. Bits [1:0] select the DMA Channel Mode Register written to by bits [7:2].

Bits[1:0]

Channel

Channel 0 (4)

Channel 1 (5)

Channel 2 (6)

Channel 3 (7)

2.5.1.3.

DR—DMA Request Register

I/O Address:

Channels 0-3—09h; Channels 4-7—0D2h

Default Value:

Bits[1:0]=undefined; Bits[7:2]=0 (CPURST or Master Clear)

Attribute:

Write Only

The Request Register is used by software to initiate a DMA request. The DMA responds to the

software request as though DREQx is asserted. These requests are non-maskable and subject to

prioritization by the priority encoder network. For a software request, the channel must be in Block

Mode. The Request Register status for DMA1 and DMA2 is output on bits [7:4] of a Status Register

read.

Bit

Description

7:3

Reserved. Must be 0

DMA Channel Service Request. 0=Resets the individual software DMA channel request bit.

1=Sets the request bit. Generation of a TC also sets this bit to 0.

1:0

DMA Channel Select. Bits [1:0] select the DMA channel mode register to program with bit 2.

Bits[1:0]

Channel

Channel 0

Channel 1 (5)

Channel 2 (6)

Channel 3 (7)

PIIX Scheda tecnica(PDF) 62 Page - Intel Corporation

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