PIIX datasheet(56/122 Pages) INTEL

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82371FB (PIIX) AND 82371SB (PIIX3)

2.4.6.

CLASSC

CLASS CODE REGISTER (Function 2) (PIIX3)

Address Offset:

−0Bh

Default Value:

010180h

Attribute:

Read Only

This register contains the device programming interface information related to the Sub-Class Code and Base

Class Code definition for the PIIX3 (function 2). This register also identifies the Base Class Code and the

function sub-class in relation to the Base Class Code.

Bit

Description

23:1

Base Class Code (BASEC). 0Ch=Universal Serial Bus controller.

15:8

Sub-Class Code (SCC). 03h=Universal Serial Bus Host Controller..

7:0

Programming Interface (PI). 00h=Capable of Universal Serial Bus operation.

2.4.7.

MLT

MASTER LATENCY TIMER REGISTER (Function 2) (PIIX3)

Address Offset:

0Dh

Default Value:

00h

Attribute:

Read/Write

MLT is an 8-bit register that controls the amount of time (in terms of PCI clocks) the USB module can do

transactions on the PCI bus. The count value is an 8-bit quantity, however MLT[3:0] are reserved and

assumed to be 0 when determining the count value. MLT is used when the USB module becomes the PCI

bus master and is cleared and suspended when PIIX3 is not asserting

FRAME#. When PIIX3 asserts

FRAME#, the counter is enabled and begins counting. If the serial bus module finishes its transaction before

count is expired the MLT value is ignored. If the count expires before the transaction completes, PIIX3

initiates a transaction termination as soon as the current transaction is completed.. The number of clocks

programmed in the MLT represents the guaranteed time slice (measured in PCI clocks) allotted to PIIX3,

after which it must surrender the bus as soon as the current transaction is completed. The default value of

MLT is 00h.

Bit

Description

7:4

Master Latency Counter Value. PIIX3 initiated PCI cycles (including multiple transactions) can

last indefinitely as long as PHLDA# remains active. However, if PHLDA# is negated after a

transaction is initiated, PIIX3 limits the duration of the transactions to the number of PCI bus

clocks specified by this field.

3:0

Reserved.

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