PIIX datasheet(92/122 Pages) INTEL

92 / 122 page

82371FB (PIIX) AND 82371SB (PIIX3)

3.3.

ISA Interface

The PIIX/PIIX3 incorporates a fully ISA Bus compatible master and slave interface. The PIIX/PIIX3 directly

drives five ISA slots without external data buffers. External transceivers are used on the SA[19:8] and SBHE#

signals to permit these signals to be used with the IDE interface (Figure 1). The ISA interface also provides

byte swap logic, I/O recovery support, wait state generation, and SYSCLK generation.

The ISA interface supports the following types of cycles:

• PCI master-initiated I/O and memory cycles to the ISA Bus

• DMA compatible cycles between main memory and ISA I/O and between ISA I/O and ISA memory

• Enhanced DMA cycles between PCI memory and ISA I/O (for motherboard devices only)

• ISA refresh cycles initiated by either the PIIX/PIIX3 or an external ISA master

• ISA master-initiated memory cycles to PCI and ISA master-initiated I/O cycles to the internal PIIX/PIIX3

registers, as shown in ISA-Compatible Register table in the Register Description section.

ALS245

SOE#,

SDIR

LA[23:17]

SA[19:8]

SBHE#

PCS#

051908_3.drw

PIIX/PIIX3

DD[15:0]

BIOSCS#,

RTCCS#,

KBCCS#

SA[7:0]

SD[15:0]

To IDE

Connector

ISA

Control

Signals

051908

Figure 1. ISA Interface

PIIX Scheda tecnica(PDF) 92 Page - Intel Corporation