PIIX datasheet(47/122 Pages) INTEL

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82371FB (PIIX) AND 82371SB (PIIX3)

2.2.24.

CTHTMR—CLOCK SCALE STPCLK# HIGH TIMER (Function 0)

Address Offset:

AEh

Default Value:

00h

Attribute:

Read/Write

The value in this register defines the duration of the STPCLK# negated period when bit 2 in the SMICNTL

The STPCLK# timer is a divide by PCI clock. The base count for a value of 0 is 42

µsec for a 50 MHz time

base, 35

µsec for a 60 MHz time base, 32 µsec for a 66 MHz time base. These numbers are determined as

follows: # of PCI clocks STPCLK# is asserted (or negated) = 1 + 1056 X (programmed value in register +1).

Bit

Description

7:0

Clock Scaling STPCLK# High Timer Value. Bits [7:0] define the duration of the STPCLK#

negated period during clock throttling.

2.3.

PCI Configuration Registers—IDE Interface (Function 1)

The PIIX/PIIX3 are multi-function devices, as indicated by bit 7 of the Header Type Register. The PCI IDE

interface function uses Function 1.

2.3.1.

VID—Vendor Identification Register (Function 1)

Address Offset:

00–01h

Default Value:

8086h

Attribute:

Read Only

The VID Register contains the vendor identification number. This register, along with the Device Identification

Bit

Description

15:0

Vendor Identification Number. This is a 16-bit value assigned to Intel

2.3.2.

DID—DEVICE IDENTIFICATION REGISTER (Function 1)

Address Offset:

02–03h

Default Value:

1230h (PIIX)

7010h (PIIX3)

Attribute:

Read Only

The DID Register contains the device identification number. This register, along with the VID Register, define

the PIIX. Writes to this register have no effect.

Bit

Description

15:0

Device Identification Number. This is a 16-bit value assigned to the PIIX.

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