PIIX datasheet(50/122 Pages) INTEL

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82371FB (PIIX) AND 82371SB (PIIX3)

Bit

Description

7:4

Master Latency Timer Count Value. PIIX-initiated PCI burst cycles can last indefinitely, as

long as PHLDA# remains active. However, if PHLDA# is negated after the burst cycle is

initiated, PIIX/PIIX3 limits the burst cycle to the number of PCI Bus clocks specified by this

field.

3:0

Reserved

2.3.8.

HEDT—HEADER TYPE REGISTER (Function 1)

Address Offset:

0Eh

Default Value:

00h

Attribute:

Read Only

The HEDT Register identifies the PIIX/PIIX3 as a multi-function device.

Bit

Description

7:0

Device Type (DEVICET). 00. Multi-function device capability for PIIX/PIIX3 is defined by the

HEDT register in Function 0.

2.3.9.

BMIBA—BUS MASTER INTERFACE BASE ADDRESS REGISTER (Function 1)

Address Offset:

20–23h

Default Value:

00000001h

Attribute:

Read/Write

This register selects the base address of a 16 byte I/O space to provide a software interface to the Bus

Master functions. Only 12 bytes are actually used (6 bytes for primary and 6 bytes for secondary).

Bit

Description

31:16

Reserved. Hardwired to 0.

15:4

Bus Master Interface Base Address. These bits provide the base address for the Bus

Master interface registers and correspond to AD[15:4].

3:2

Reserved. Hardwired to 0.

Reserved.

Resource Type Indicator (RTE)—RO. This bit is hardwired to 1 indicating that the base

address field in this register maps to I/O space.

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