PIIX datasheet(74/122 Pages) INTEL

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82371FB (PIIX) AND 82371SB (PIIX3)

2.5.3.9.

ELCR1—Edge/Level Triggered Register

I/O Address:

INT CNTRL-1—4D0h

Default Value:

00h

Attribute:

Read/Write

ELCR1 register allows IRQ3 - IRQ7 to be edge or level programmable on an interrupt by interrupt basis.

IRQ0, IRQ1 and IRQ2 are not programmable and are always edge sensitive.

Bit

Description

IRQ7 ECL. 0 = edge triggered mode; 1 = level sensitive mode.

IRQ6 ECL. 0 = edge triggered mode; 1 = level sensitive mode.

IRQ5 ECL. 0 = edge triggered mode; 1 = level sensitive mode.

IRQ4 ECL. 0 = edge triggered mode; 1 = level sensitive mode.

IRQ3 ECL. 0 = edge triggered mode; 1 = level sensitive mode.

2:0

Reserved. Must be 0.

2.5.3.10.

ELCR2—Edge/Level Triggered Register

I/O Address:

INT CNTRL-2—4D1h

Default Value:

00h

Attribute:

Read/Write

ELCR2 register allows IRQ[15,14,12:9] to be edge or level programmable on an interrupt by interrupt basis.

Note that, IRQ[13,8#] are not programmable and are always edge sensitive.

Bit

Description

IRQ15 ECL. 0 = edge triggered mode; 1 = level sensitive mode.

IRQ14 ECL. 0 = edge triggered mode; 1 = level sensitive mode.

Reserved. Must be 0.

IRQ12 ECL. 0 = edge triggered mode; 1 = level sensitive mode.

IRQ11 ECL. 0 = edge triggered mode; 1 = level sensitive mode.

IRQ10 ECL. 0 = edge triggered mode; 1 = level sensitive mode.

IRQ9 ECL. 0 = edge triggered mode; 1 = level sensitive mode.

Reserved. Must be 0.

PIIX Scheda tecnica(PDF) 74 Page - Intel Corporation