PIIX datasheet(12/122 Pages) INTEL

12 / 122 page

82371FB (PIIX) AND 82371SB (PIIX3)

Signal Name

Type

Description

IORDY

IO CHANNEL READY: This input signal is directly driven by the

corresponding signal on up to two IDE connectors (primary and

secondary).

SOE#

SYSTEM ADDRESS TRANSCEIVER OUTPUT ENABLE: This signal

controls the output enables of the ’245 transceivers that interface the

DD[15:0] signals to the SA[19:8], SBHE#, PCS# and APICCS# (PIIX3

only) signals.

SDIR

SYSTEM ADDRESS TRANSCEIVER DIRECTION: This signal controls

the direction of the ’245 transceivers that interface the DD[15:0] signals

to the SA[19:8], SBHE#, PCIS, and APICCS# (PIIX3 only), signals.

Default condition is high (transmit). When an ISA Bus master is granted

use of the bus, the transceivers are turned around to drive the ISA

address [19:8] on DD[15:3]. The address can then be latched by the

PIIX/PIIX3. In this case, the SDIR signal is low (receive). The SOE# and

SDIR signals taken together as a group can assume one of three states:

SOE#

SDIR

State

PCI to ISA transaction

PCI to IDE

ISA Bus master

Signals Buffered from LA[23:17]

These signals are buffered from the LA[23:17] lines by an ALS244 tri-state buffer. The output enable of this

buffer is tied asserted. These signals are set up with respect to the IDE command strobes (DIOR# and IOW#)

and are valid throughout I/O transactions targeting the ATA register block(s).

Signal Name

Type

Description

LA23/

CS1S

I/O

CHIP SELECT: CS1S is for the ATA command register block and

corresponds to the inverted CS1FX# on the secondary IDE connector.

CS1S is inverted externally (see PCI Local Bus IDE section).

LA22/

CS3S

I/O

CHIP SELECT: CS3S is for the ATA control register block and

corresponds to the inverted CS3FX# on the secondary IDE connector.

CS3S is inverted externally (see PCI Local Bus IDE section).

LA21/

CS1P

I/O

CHIP SELECT: CS1P is for the ATA command register block and

corresponds to the inverted CS1FX# on the primary IDE connector. CS1P

is inverted externally (see PCI Local Bus IDE section).

LA20/

CS3P

I/O

CHIP SELECT: CS3P is for the ATA control register block and

corresponds to the inverted CS3FX# on the primary IDE connector. CS3P

is inverted externally (see PCI Local Bus IDE section).

LA[19:17]

DA[2:0]

I/O

DISK ADDRESS: DA[2:0] are used to indicate which byte in either the

ATA command block or control block is being addressed.

PIIX Scheda tecnica(PDF) 12 Page - Intel Corporation

PIIX Scheda tecnica(HTML) 12 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL