PIIX datasheet(90/122 Pages) INTEL

90 / 122 page

82371FB (PIIX) AND 82371SB (PIIX3)

NOTES:

Except accesses to programmed memory hole.

Forward to main memory if bit 6=0 in the XBCS Register and bit 3=1 in the TOM Register.

Forward to main memory if bit 1=0 in the TOM Register.

3.1.3.

BIOS MEMORY

The PIIX/PIIX3 supports 512 Kbytes of BIOS space. This includes the normal 128-Kbyte space plus an

additional 384-Kbyte BIOS space (known as the extended BIOS area). The XBCS Register provides BIOS

space access control. Access to the lower 64-Kbyte block of the 128-Kbyte space and the extended BIOS

space can be individually enabled/disabled. In addition, write protection can be programmed for the entire

BIOS space.

PCI Access to BIOS Memory

The 128-Kbyte BIOS memory space is located at 000E0000–000FFFFFh (top of 1 Mbyte) and is aliased at

FFFE0000h (top of 4 Gbytes). This 128-Kbyte byte block is split into two 64-Kbyte blocks. Accesses to the

top 64 Kbytes (000F0000–000FFFFFh) are forwarded to the ISA Bus and BIOSCS# is always generated.

Accesses to the bottom 64 Kbytes (000E0000–000EFFFFh) are forwarded to the ISA Bus and BIOSCS# is

only generated when this BIOS region is enabled. 1.If this BIOS region is enabled (bit 6=1 in the XBCS

ISA and BIOSCS# generated. If disabaled, these accesses are not forwarded to ISA and BIOSCS# is not

generated.

The additional 384-Kbyte region resides at FFF80000–FFFDFFFFh. If this BIOS region is enabled (bit 7=1 in

the XBCS Register), these accesses (FFF80000h–FFFDFFFFh) are forwarded to ISA and BIOSCS#

generated. If disabled, these accesses are not forwarded to ISA and BIOSCS# not generated.

ISA Access to BIOS Memory

The PIIX/PIIX3 confines all ISA-initiated BIOS accesses to the top 64 Kbytes of the 128-Kbyte region

(F0000–FFFFFh) to the ISA Bus, even if BIOS is shadowed in main memory. Accesses to the bottom 64

Kbytes of the 128-Kbyte BIOS region (E0000–EFFFFh) are confined to the ISA Bus, when this region is

enabled. When the BIOS region is disabled, accesses are forwarded to main memory.

Accesses to the top 64-Kbyte BIOS region always generates BIOSCS#. Accesses to the bottom 64-Kbyte

BIOS region generate BIOSCS#, when this region is enabled.

3.2.

PCI Interface

The PIIX/PIIX3 incorporates a fully PCI Bus compatible master and slave interface. As a PCI master, the

PIIX/PIIX3 runs cycles on behalf of DMA, ISA masters, or a bus master IDE. As a PCI slave, the PIIX/PIIX3

accepts cycles initiated by PCI masters targeted for the PIIX's internal register set or the ISA bus. The

PIIX/PIIX3 directly supports the PCI interface running at either 25 MHz, 30 MHz, or 33 MHz.

3.2.1.

TRANSACTION TERMINATION

The PIIX/PIIX3 supports the standard PCI cycle terminations as described in the PCI Local Bus specification.

PIIX/PIIX3 As Master—Master-Initiated Termination: The PIIX/PIIX3 supports three forms of master-

initiated termination: 1.) Normal termination of a completed transaction, 2.) Normal termination of an

incomplete transaction due to timeout (applies to line buffer operations-IDE Bus Master, 3.) Abnormal

termination due to the slave not responding to the transaction (Abort).

PIIX Scheda tecnica(PDF) 90 Page - Intel Corporation

PIIX Scheda tecnica(HTML) 90 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL