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H8S/2214 Scheda tecnica(PDF) 328 Page - Renesas Technology Corp |
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H8S/2214 Scheda tecnica(HTML) 328 Page - Renesas Technology Corp |
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328 / 936 page ![]() Section 8 Data Transfer Controller (DTC) Rev.4.00 Sep. 18, 2008 Page 268 of 872 REJ09B0189-0400 Register information start address Register information Chain transfer DTC vector address Figure 8.4 Correspondence between DTC Vector Address and Register Information 8.3.4 Location of Register Information in Address Space Figure 8.5 shows how the register information should be located in the address space. Locate the MRA, SAR, MRB, DAR, CRA, and CRB registers, in that order, from the start address of the register information (contents of the vector address). In the case of chain transfer, register information should be located in consecutive areas. Locate the register information in the on-chip RAM (addresses: H'FFEBC0 to H'FFEFBF). Register information start address Chain transfer Register information for 2nd transfer in chain transfer MRA SAR MRB DAR CRA CRB 4 bytes Lower address CRA CRB Register information MRA 01 2 3 SAR MRB DAR Figure 8.5 Location of Register Information in Address Space |
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