H8SSLASH2214 datasheet(331/936 Pages) RENESAS

Il numero della parte	H8S/2214

Spiegazioni elettronici	16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

PDF	936 Pages

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Produttore elettronici	RENESAS [Renesas Technology Corp]

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Section 8 Data Transfer Controller (DTC)

Rev.4.00 Sep. 18, 2008 Page 271 of 872

REJ09B0189-0400

8.3.7

Block Transfer Mode

In block transfer mode, one operation transfers one block of data. Either the transfer source or the

transfer destination is designated as a block area.

The block size is 1 to 256. When the transfer of one block ends, the initial state of the block size

counter and the address register specified as the block area is restored. The other address register

is then incremented, decremented, or left fixed.

From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a

CPU interrupt is requested.

Table 8.7 lists the register information in block transfer mode and figure 8.8 shows memory

mapping in block transfer mode.

Table 8.7

Name

Abbreviation

Function

DTC source address register

SAR

Designates source address

DTC destination address register

DAR

Designates destination address

DTC transfer count register AH

CRAH

Holds block size

DTC transfer count register AL

CRAL

Designates block size count

DTC transfer count register B

CRB

Transfer count

H8S/2214 Scheda tecnica(PDF) 331 Page - Renesas Technology Corp