H8SSLASH2214 datasheet(409/936 Pages) RENESAS

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Section 9 I/O Ports

Rev.4.00 Sep. 18, 2008 Page 349 of 872

REJ09B0189-0400

9.12.2

Table 9.22 shows the port F register configuration.

Table 9.22

Port F Registers

Name

Abbreviation

R/W

Initial Value

Address*

Port F data direction register

PFDDR

H'80/H'00*

H'FE3E

Port F data register

PFDR

R/W

H'00

H'FF0E

Port F register

PORTF

Undefined

H'FFBE

Notes: 1. Lower 16 bits of the address.

2. Initial value depends on the mode. Initialized to H'80 in modes 4 to 6, and to H'00 in

mode 7.

(1) Port F Data Direction Register (PFDDR)

PF7DDR

PF6DDR

PF5DDR

PF4DDR

PF3DDR

PF0DDR

PF2DDR

PF1DDR

Bit

Modes 4 to 6 :

Initial value

R/W

Mode 7

Initial value

R/W

PFDDR is an 8-bit write-only register, the individual bits of which specify input or output for the

pins of port F. PFDDR cannot be read; if it is, an undefined value will be read.

Setting a PFDDR bit to 1 makes the corresponding port C pin an output pin, while clearing the bit

to 0, makes the pin an input pin. Since this register is a write-only register, do not use bit

manipulation instructions to write to this register. See section 2.10.4, Access Methods for

Registers with Write-Only Bits.

PFDDR is initialized to H'80 (modes 4 to 6) or H'00 (mode 7) by a power-on reset and in hardware

standby mode. It retains its previous state after a manual reset and in software standby mode. The

OPE bit in SBYCR is used to select whether the bus control output pins retain their output state or

become high-impedance when a transition is made to software standby mode.

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